As the integration of a semiconductor device becomes high, the spacing between interconnections in the semiconductor device becomes narrow; and there is a risk that the insulation breakdown voltage may decrease and the interconnection resistance and parasitic capacitance may increase. For example, when performing large-scale integration of memory cells of a NAND nonvolatile memory device, bit lines that electrically connect memory strings to sense amplifiers are made narrower; and the spacing of the bit lines is made narrower. Thereby, a decrease of the operation speed of the memory device and/or short failures between the bit lines may occur.